Aldec Active-HDL Student Edition

Aldec Active-HDL Student Edition 9.1

Designs, creates, and simulates the field-programmable gate arrays
3.2  (10 votes)
9.1 (See all)
Create designs and simulations with more than 120+ EDA and field-programmable gate arrays tools that will assist in design entry, simulation, synthesis and implementation flows. The Unified Team-based Design Management module maintains a connection between local and remote design teams. Students have pre-compiled FPGA vendor libraries at their disposal as well and "load and go" licenses.

Active-HDL Student Edition is a mixed language design entry and simulation tool offered at no cost by Aldec to the students to use during their course work.
Key Features of Active-HDL Student Edition:
- Mixed language simulator
- Multi-FPGA & EDA Tool Design Flow Manager
- Graphical Design entry & editing
- Code2Graphics and Graphics2Code
- Pre-compiled FPGA vendor libraries

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